In various communication networks, network elements such as a switch, router or Network Interface Controller (NIC), interconnect using ports. Each port comprises one or more Serializer/Deserializer (SERDES) devices for serially transmitting and receiving traffic to and from the communication network via respective physical lanes.
Network elements having multi-lane ports are known in the art. For example, U.S. Pat. No. 8,601,297 describes energy proportional solutions for computer networks such as data centers. Congestion sensing heuristics are used to adaptively route traffic across links. Traffic intensity is sensed and links are dynamically activated as they are needed. As the offered load is decreased, the lower channel utilization is sensed and the link speed is reduced to save power. Flattened butterfly topologies can be used in a further power saving approach. Switch mechanisms exploit the topology's capabilities by reconfiguring link speeds on-the-fly to match bandwidth and power with the traffic demand. For instance, the system may estimate the future bandwidth needs of each link and reconfigure its data rate to meet those requirements while consuming less power. In one configuration, a mechanism is provided where the switch tracks the utilization of each of its links over an epoch, and then makes an adjustment at the end of the epoch.
Multi-lane ports for 40 Gbps and 100 Gbps are specified, for example, in “802.3ba-2010—IEEE Standard for Information technology—Local and metropolitan area networks—Specific requirements—Part 3: CSMA/CD Access Method and Physical Layer Specifications Amendment 4: Media Access Control Parameters, Physical Layers, and Management Parameters for 40 Gb/s and 100 Gb/s Operation,” Jun. 22, 2010, which is incorporated herein by reference.